On-chip trace data information sources for debugging trace information data e.g. instruction trace data information and data trace information relating to data transfer information and signaling information, require an increasing amount of bandwidth due to an increased number of processor cores and on-chip busses and rising clock frequencies. Although the cost of outputting trace over chip/package pins is declining, it is declining less rapidly than the cost of transistor components such as logic, and random access memory cells. Therefore, the price for outputting high bandwidth over pins is becoming prohibitively expensive.
It is possible to output compressed trace data information over package pins, i.e. off-chip traces, e.g. over the Nexus ISTO-5001 standard or ARM ETM, up to a limited number of cores and clock frequency. For higher bandwidth, High-Speed Serial Ports (HSSP) are currently being evaluated in the industry. HSSP will increase the bandwidth per pin, however significant costs are incurred on the chip, e.g. PHY, GigaHz phase-locked loop circuits, and for the tooling. Another conventional approach is to implement an on-chip trace, wherein the on-chip components, e.g. logic, and random access memory scale with process technology. The on-chip approach allows a very high bandwidth for tracing but only over a short duration due to the limited on-chip trace buffer.